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ds04-21359-2e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 1.2 ghz prescaler MB15E03SL n description the fujitsu MB15E03SL is a serial input phase locked loop (pll) frequency synthesizer with a 1.2 ghz prescaler. the 1.2 ghz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. the supply voltage range is between 2.4 v and 3.6 v. the MB15E03SL uses the latest bicmos process, as a result, the supply current is typically 2.0 ma at 2.7 v. a refined charge pump supplies a well balanced output currents of 1.5 ma or 6 ma. the charge pump current is selectable by serial data. MB15E03SL is ideally suited for wireless mobile communications, such as gsm. n features ? high frequency operation: 1.2 ghz max ? low power supply voltage: v cc = 2.4 v to 3.6 v ? ultra low power supply current: i cc = 2.0 ma typ. (v cc = vp = 2.7 v, ta = +25 c, in locking state) i cc = 2.5 ma typ. (v cc = vp = 3 v, ta = +25 c, in locking state) ? direct power saving function: power supply current in power saving mode typ. 0.1 m a (v cc = vp = 3 v, ta = +25 c), max. 10 m a (v cc = vp = 3 v) ? dual modulus prescaler: 64/65 or 128/129 ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? selectable charge pump current ? on-chip phase control for phase comparator ? operating temperature: ta = C40 to +85 c ? pin compatible with mb15e03, mb15e03l n packages 16-pin, plastic ssop (fpt-16p-m05) 16-pad, plastic bcc (lcc-16p-m02)
2 MB15E03SL n pin assignments osc in osc out v p v cc d o gnd xfin fin f r f p ld/fout zc ps le data clock 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 top view osc out v p v cc d o gnd xfin f p ld / fout zc ps le data osc in f r fin clock 1 2 3 4 5 678 9 10 11 12 13 14 15 16 top view (fpt-16p-m05) (lcc-16p-m02) 16-pin ssop 16-pad bcc
3 MB15E03SL n pin description pin no. pin name i/o descriptions ssop bcc 116osc in i programmable reference divider input. oscillator input connection to a tcxo. 21osc out o oscillator output. 32v p power supply voltage input for the charge pump. 43v cc power supply voltage input. 54d o o charge pump output. phase of the charge pump can be selected via programming of the fc bit. 6 5 gnd ground. 7 6 xfin i prescaler complementary input which should be grounded via a capacitor. 87fini prescaler input. connection to an external vco should be done via ac coupling. 98clocki clock input for the 19-bit shift register. data is shifted into the shift register on the rising edge of the clock. (open is prohibited.) 10 9 data i serial data input using binary code. the last bit of the data is a control bit. (open is prohibited.) 11 10 le i load enable signal input. (open is prohibited.) when le is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. 12 11 ps i power saving mode control. this pin must be set at l at power-on. (open is prohibited.) ps = h; normal mode ps = l; power saving mode 13 12 zc i forced high-impedance control for the charge pump (with internal pull up resistor.) zc = h; normal do output. zc = l; do becomes high impedance. 14 13 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected via programming of the lds bit. lds = h; outputs fout (fr/fp monitoring output) lds = l; outputs ld (h at locking, l at unlocking.) 15 14 f po phase comparator n-channel open drain output for an external charge pump. phase can be selected via programming of the fc bit. 16 15 f ro phase comparator cmos output for an external charge pump. phase can be selected via programming of the fc bit.
4 MB15E03SL n block diagram clock data fin le osc out osc in reference oscillator circuit phase comparator lock detector ld/fr/fp selector binary 14-bit reference counter binary 7-bit swallow counter binary 11-bit programmable counter 14-bit latch 4-bit latch 19-bit shift register intermittent mode control (power save) 1-bit cotrol latch prescaler 64 / 65, 128 / 129 7-bit latch charge pump current switch 11-bit latch ps d o v p f r ld / fout f p xfin gnd v cc md zc c n t sw fc cs lds fr fp (16) (1) (2) (3) (4) (5) (6) (7) (15) (14) (13) (12) (11) (10) (9) (8) 16 15 14 13 12 11 10 9 8 : ssop ( ): bcc 7 6 5 4 3 2 1
5 MB15E03SL n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol condition rating unit remark min. max. power supply voltage v cc C0.5 4.0 v v p v cc 6.0 v input voltage v i C0.5 v cc +0.5 v output voltage v o except do gnd v cc v v o do gnd v p v storage temperature tstg C55 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.4 3.0 3.6 v v p v cc 5.5v input voltage v i gnd v cc v operating temperature ta C40 +85 c
6 MB15E03SL n electrical characteristics (v cc = 2.4 to 3.6 v, ta = C40 to +85 c) parameter symbol condition value unit min. typ. max. power supply current* 1 i cc *1 v cc = v p = 2.7 v (v cc = v p = 3.0 v) 2.0 (2.5) ma power saving current i ps zc = h or open 0.1 *2 10 m a operating frequency fin fin 100 1200 mhz osc in osc in 340mhz input sensitivity fin *3 vfin 50 w system (refer to the measurment cicuit.) C15 +2 dbm osc in *3 v osc 0.5v cc vp-p h level input voltage data, clock, le, ps, zc v ih v cc 0.7 v l level input voltage v il v cc 0.3 h level input current data, clock, le, ps i ih *4 C1.0+1.0 m a l level input current i il *4 C1.0+1.0 h level input current osc in i ih 0 +100 m a l level input current i il *4 C1000 h level input current zc i ih *4 C1.0+1.0 m a l level input current i il *4 pull up input C100 0 l level output voltage f pv ol open drain output 0.4 v h level output voltage f r, ld/fout v oh v cc = v p = 3 v, i oh = C1 ma v cc C 0.4 v l level output voltage v ol v cc = v p = 3 v, i ol = 1 ma 0.4 h level output voltage do v doh v cc = v p = 3 v, i doh = C0.5 ma v p C 0.4 v l level output voltage v dol v cc = v p = 3 v, i dol = 0.5 ma 0.4 high impedance cutoff current do i off v cc = v p = 3 v, v off = 0.5 v to v p C 0.5 v 2.5na l level output current f pi ol open drain output 1.0 ma h level output current f r, ld/fout i oh C1.0 ma l level output current i ol 1.0 h level output current do i doh *4 v cc = 3 v, v p = 3 v, v do = v p /2 ta = + 2 5 c cs bit = h C6.0 ma cs bit = l C1.5 l level output current i dol cs bit = h 6.0 cs bit = l 1.5 charge pump current rate i dol /i doh i domt *5 v dd = v p /2 3 % vs v do i dovd *6 0.5 v v do v p C 0.5 v 10 % vs ta i dota *7 C 40 c ta +85 c10%
7 MB15E03SL *1: conditions; fin = 1200 mhz, fosc = 12 mhz, ta = +25 c, in locking state. *2: v cc = v p = 3.0 v, fosc = 12.8 mhz, ta = +25 c, in power saving mode *3: ac coupling. 1000 pf capacitor is connected under the condition of min. operating frequency. *4: the symbol C (minus) means direction of current flow. *5: v cc = v p = 3.0 v, ta = +25 c (|i 3 | C |i 4 |) / [(|i 3 | + |i 4 |) /2] 100(%) *6: v cc = v p = 3.0 v, ta = +25 c [(|i 2 | C |i 1 |) /2] / [(|i 1 | + |i 2 |) /2] 100(%) (applied to each i dol , i doh ) *7: v cc = v p = 3.0 v, v do = v p /2 (|i do(+85 c) C i do(C40 c) | /2) / (|i do(+85 c) + i do(C40 c) | /2) 100(%) (applied to each i dol , i doh ) i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vp / 2 charge pump output voltage (v) vp vp - 0.5 v
8 MB15E03SL n functional description 1. pulse swallow function the divide ratio can be calculated using the following equation: f vco = [(m n) + a] f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) m : preset divide ratio of the dual modulus prescaler (64 or 128) 2. serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the le pin is taken high, stored data is latched according to the control bit data as follows: table 1. control bit (1) shift register configuration control bit (cnt) destination of serial data h for the programmable reference divider l for the programmable divider 12345678910111213141516171819 c n t r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 sw fc lds cs programmable reference counter msb data flow cnt : control bit [table 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (3 to 16,383) [table 2] sw : divide ratio setting bit for the prescaler (64/65 or 128/129) [table 5] fc : phase control bit for the phase comparator [table 8] lds : ld/fout signal select bit [table 7] cs : charge pump current select bit [table 6] note: start data input with msb first. lsb
9 MB15E03SL table 2. binary 14-bit programmable reference counter data setting note: divide ratio less than 3 is prohibited. table 3. binary 11-bit programmable counter data setting note: divide ratio less than 3 is prohibited. divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 3 00000000000011 4 00000000000100 16383 11111111111111 divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 3 00000000011 4 00000000100 2047 1 1 1 1 1 1 1 1 1 1 1 12345678910111213141516171819 c n t a 1 a 2 a 3 a 4 a 5 a 6 a 7 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 programmable counter lsb msb data flow cnt : control bit [table 1] n1 to n11: divide ratio setting bits for the programmable counter (3 to 2,047) [table 3] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table 4] note: start data input with msb first.
10 MB15E03SL table 4. binary 7-bit swallow counter data setting table 5. prescaler data setting table 6. charge pump current setting table 7. ld/fout output select data setting (2) relation between the fc input and phase characteristics the fc bit changes the phase characteristics of the phase comparator. both the internal charge pump output level (d o ) and the phase comparator output ( f r, f p) are reversed according to the fc bit. also, the monitor pin (fout) output is controlled by the fc bit. the relationship between the fc bit and each of d o , f r, and f p is shown below. table 8. fc bit data setting (lds = h) * : high impedance divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw prescaler divide ratio h 64/65 l 128/129 cs current value h 6.0 ma l 1.5 ma lds ld/ f out output signal h fout signal l ld signal fc = high fc = low d o f r f p ld/fout d o f r f p ld/fout fr > f p hll fout = fr lhz* fout = fp fr < f p lhz* hll fr = f p z* l z* z* l z*
11 MB15E03SL when designing a synthesizer, the fc pin setting depends on the vco and lpf characteristics. 3. do output control table 9. zc pin setting 4. power saving mode (intermittent mode control circuit) table 10. ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the signal pll, the lock detector, ld, remains high, indicating a locked condition. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. note: when power (v cc ) is first applied, the device must be in standby mode, ps = low, for at least 1 m s. zc pin do output h normal output l high impedance ps pin status h normal mode l power saving mode (1) vco output frequency lpf output voltage (2) * : when the lpf and vco characteristics are similar to (1), set fc bit high. * : when the vco characteristics are similar to (2), set fc bit low. pll lpf vco
12 MB15E03SL note: ps pin must be set l for power-on . on off v cc clock data le ps (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps = l (power saving mode) at power on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps: l ? h) 100 ns later after setting serial data.
13 MB15E03SL n serial data input timing data clock le msb lsb control bit invalid data 2nd data 1st data t 1 t 2 t 3 t 6 t 5 t 4 t 7 ~ ~ ~ ~ note: le should be l when the data is transferred into the shift register. parameter min. typ. max. unit t1 20 ns t2 20 ns t3 30 ns t4 30 ns parameter min. typ. max. unit t5 100 ns t6 20 ns t7 100 ns on the rising edge of the clock, one bit of data is transferred into the shift register.
14 MB15E03SL n phase comparator output waveform fr fp ld d o h z l l z h d o t wu t wl notes: 1. phase error detection range: C2 p to +2 p 2. pulses on do output signal during locked state are output to prevent dead zone. 3. ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. 4. t wu and t wl depend on osc in input frequency. t wu > 2/fosc (s) (e. g. t wu > 156.3 ns, foscin = 12.8 mhz) t wu < 4/fosc (s) (e. g. t wl < 312.5 ns, foscin = 12.8 mhz) 5. ld becomes high during the power saving mode (ps = l). [fc = h] [fc = l]
15 MB15E03SL n measurment circuit (for measuring input sensitivity fin/osc in ) s g 50 w 1000 pf s g 50 w 1000 pf 0.1 m f 0.1 m f 86 43 1 9101112 14 75 2 13 15 16 1000 pf v cc fin xfin gnd d o v cc v p osc out osc in clock note: 16-pin ssop controller (setting divide ratio) oscilloscope data le ps zc ld/fout f p f r
16 MB15E03SL n typical characteristics 1. fin input sensitivity 2. osc in input sensitivity 10 0 0 500 1000 1500 2000 - 10 - 20 - 30 - 40 - 50 ta = +25 c v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v input sensitivity - input frequency (prescaler 64/65) input frequency fin (mhz) input sensitivity vfin (dbm) spec v cc = 2.4 v v cc = 3.0 v v cc = 3.6 v 0 50 100 ta = +25 c input sensitivity - input frequency input frequency f osc (mhz) 10 0 - 10 - 20 - 30 - 40 - 50 - 60 input sensitivity v osc (dbm) spec
17 MB15E03SL 3. do output current 10.00 i oh i ol 2.000 /div 0 0 4.800 .6000/div - 10.00 v do - i do charge pump output voltage v do (v) charge pump output current i do (ma) ta = +25 c v cc = 3.0 v vp = 3.0 v 4.800 - 10.00 v do - i do charge pump output voltage v do (v) charge pump output current i do (ma) 10.00 i oh i ol 2.000 /div 0 0 .6000/div ta = +25 c v cc = 3.0 v vp = 3.0 v 1.5 ma mode 6.0 ma mode
18 MB15E03SL 4. fin input impedance 5. osc in input impedance 297.63 w - 656.53 w 100 mhz 24.523 w - 185.55 w 400 mhz 9.3789 w - 77.168 w 800 mhz 10.188 w - 33.143 w 1.2 ghz 1 : 2 : 3 : 4 : 4 3 2 start 100.000 000 mhz stop 1 200.000 000 mhz 1 9.063 k w - 3.113 k w 3 mhz 3.8225 w - 4.6557 k w 10 mhz 1.5735 w - 3.2154 k w 20 mhz 405.69 w - 1.8251 k w 40 mhz 1 : 2 : 3 : 4 : 3 1 start 3.000 000 mhz stop 40.000 000 mhz 4 3
19 MB15E03SL n reference information (continued) s.g. osc in fin vco d o lpf spectrum analyzer f vco = 810.425 mhz k v = 17 mhz/v fr = 25 khz f osc = 14.4 mhz exp current: 6.0 ma 4.2 k w 47000 pf 9.1 k w 4700 pf 1500 pf vco do ?lpf
20 MB15E03SL (continued) atten center span 20.00 khz 810.42500 mhz rbw 100 hz * * swp vbw 100 hz 3.00 sec d mkr - 53.00 db 10 db rl 2.23 khz - 5.0 dbm 73.0 dbc/hz atten center span 200.0 khz 810.42500 mhz rbw 1.0 khz swp vbw 1.0 khz 1.00 sec d mkr - 79.83 db 10 db rl 25.0 khz - 5.0 dbm 79.8 dbc ** ta = +25 c ? pll reference leakage ? pll phase noise ta = +25 c
21 MB15E03SL (continued) 830.00500 mhz 2.00 khz/div 829.99500 mhz 5.0000000 ms 830.00500 mhz 2.00 khz/div 829.99500 mhz 5.0000000 ms 850.00500 mhz 10.00000 hz/div 810.00000 mhz 5.0000000 ms 860.00000 mhz 10.00000 hz/div 810.00000 mhz 5.0000000 ms pll lock up time 810.425 mhz ? 826.425 1khz lch ? hch 1.40 ms pll lock up time 826.425 mhz ? 810.425 1khz hch ? lch 1.52 ms
22 MB15E03SL n application example 10 k w 0.1 m f 1000 pf output v p 12 k w 12 k w 10 k w lpf vco 16 15 13 12 11 10 9 123 4 56 78 0.1 m f 1000 pf lock detect. MB15E03SL from a controller f r f p ld/fout zc clock ps le data osc in osc out v p v cc d o gnd xfin fin tcxo 1000 pf vp: 5.5 v max notes:1. ssop-16 2. in case of using a crystal resonator, it is necessary to optimize matching between the crystal and this lsi, and perform detailed system evaluation. it is recommended to consult with a supplier of the crystal resonator. (reference oscillator circuit provides its own bias, feedback resistor is 100 k w (typ).)
23 MB15E03SL n usage precautions to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting device into or removing device from a socket. -protect leads with a conductive sheet when transporting a board-mounted device. n ordering information part number package remarks MB15E03SLpfv1 16-pin, plastic ssop (fpt-16p-m05) MB15E03SLpv 16-pad, plastic bcc (lcc-16p-m02)
24 MB15E03SL n package dimensions (continued) +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 5.000.10(.197.004) 4.55(.179)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f16013s-2c-4 c dimensions in mm (inches ) 16-pin, plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion.
25 MB15E03SL (continued) c 1996 fujitsu limited c16013s-1c-1 0.3250.10 (.013.004) 0.65(.026)typ 3.40(.134)typ 1.725(.068) typ 1.15(.045)typ "b" "a" 0.400.10 (.016.004) 2.45(.096) 0.80(.032) typ typ 3.400.10 (.1339.0039) 4.550.10 (.179.004) 0.80(.032)max 0.0850.04 (.003.002) (stand off) 0.40(.016) 45? e-mark 0.05(.002) 6 9 1 14 9 14 1 6 0.600.10 (.024.004) 0.600.10 (.024.004) details of "b" part 0.400.10 (.016.004) 0.750.10 (.030.004) details of "a" part dimensions in mm (inches ) (mounting height) 16-pad, plastic bcc (lcc-16p-m02)
26 MB15E03SL memo
27 MB15E03SL memo
28 MB15E03SL fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9811 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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